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sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processors adsp-21362/adsp-21363/adsp- 21364/adsp-21365/adsp-21366 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 all rights reserved. summary high performance 32-bit/40-bit floating point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture on-chip memory3m bits of on-chip sram code compatible with all other members of the sharc family the adsp-2136x processors are av ailable with up to 333 mhz core instruction rate with unique audiocentric peripherals such as the digital applications interface, s/pdif trans- ceiver, dtcp (digital tran smission content protection protocol), serial ports, pr ecision clock generators, and more. for complete ordering information, see ordering guide on page 54 . dedicated audio components s/pdif-compatible digital audio receiver/transmitter 8 channels of asynchronous sample rate converters (src) 16 pwm outputs configured as four groups of four outputs rom-based security features include: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios available in 136-ball csp_bga and 144-lead lqfp_ep packages figure 1. function al block diagram internal memory i/f block 0 ram/rom b0d 64-bit instruction cache 5 stage sequencer pex pey pmd 64-bit core bus cross bar block 1 ram/rom block 2 ram block 3 ram dag1/2 timer iod bus mtm/ dtcp peripheral bus 32-bit internal memory dmd 64-bit peripheral bus b1d 64-bit b2d 64-bit b3d 64-bit dai peripherals peripherals simd core s core flags spi pwm 3 - 0 pp pp pin mux pdap/ idp7-0 asrc 3 - 0 timer 2 - 0 core flags s/pdif tx/rx pcg a - b spi b sport 5 - 0 dai routing/pins iod 32-bit flagx/irqx/ tmrexp jtag pmd 64-bit dmd 64-bit
rev. g | page 2 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 table of contents summary ............................................................... 1 dedicated audio components .................................... 1 revision history ...................................................... 2 general description ................................................. 3 sharc family core architecture ............................ 4 family peripheral architecture ................................ 6 i/o processor features ........................................... 8 system design ...................................................... 8 development tools ............................................... 9 additional information ........................................ 10 related signal chains .......................................... 10 pin function descriptions ....................................... 11 specifications ........................................................ 14 operating conditions .......................................... 14 electrical characteristics ....................................... 14 package information ............................................ 15 esd caution ...................................................... 15 maximum power dissipation ................................. 15 absolute maximum ratings ................................... 15 timing specifications ........................................... 15 output drive currents ......................................... 44 test conditions .................................................. 44 capacitive loading .............................................. 44 thermal characteristics ........................................ 45 144-lead lqfp_ep pin configurations ... .................... 46 136-ball bga pin configurations . .............................. 48 package dimensions ............................................... 51 surface-mount design .......................................... 52 automotive products .............................................. 53 ordering guide ..................................................... 54 revision history 3/11rev. f to rev. g revised s/pdif transmitter input data timing ............. 38 revised table 45 , added figure 43 and figure 44 in 144-lead lqfp_ep pin configurations .................................... 46 added an additional model to automotive products ....... 53
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 3 of 56 | march 2011 general description the adsp-2136x sharc ? processor is a member of the simd sharc family of dsps that feat ure analog devices, inc., super harvard architecture. the proce ssor is source code-compatible with the adsp-2126x and adsp-2 116x dsps, as well as with first generation adsp-2106x sharc processors in sisd (single-instruction, single-d ata) mode. the adsp-2136x are 32-/40-bit floating-point proc essors optimized for high performance automotive audio applications. they contain a large on-chip sram and rom, mult iple internal buses to elim- inate i/o bottlenecks, and an innovative digital audio interface (dai). as shown in the functional block diagram on page 1 , the adsp-2136x uses two computationa l units to deliver a signifi- cant performance increase over the previous sharc processors on a range of signal processing algorithms. with its simd com- putational hardware, the adsp-2136x can perform two gflops running at 333 mhz. table 1 shows performance benchm arks for these devices. table 2 shows the features of the in dividual product offerings. the diagram on page 1 shows the two clock domains that make up the adsp-2136x processors. th e core clock domain contains the following features: ? two processing elements, each of which comprises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ? one periodic interval timer with pinout ?on-chip sram (3m bit) ? on-chip mask-programmable rom (4m bit) ? jtag test access port for em ulation and boundary scan. the jtag provides software debug through user break- points, which allow flexible exception handling. the diagram on page 1 also shows the following architectural features: ? i/o processor that handles 32-bit dma for the peripherals ? six full duplex serial ports ? two spi-compatible interface portsprimary on dedi- cated pins, secondary on dai pins ? 8-bit or 16-bit parallel port th at supports interfaces to off- chip memory peripherals ? digital audio interface that includes two precision clock generators (pcg), an input da ta port (idp), an s/pdif receiver/transmitter, 8-channel asynchronous sample rate converter, dtcp cipher, six seri al ports, eight serial inter- faces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (sru) table 1. benchmarks (at 333 mhz) benchmark algorithm speed (at 333 mhz) 1024 point complex fft (radix 4, with reversal) 27.9 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode. 1.5 ns iir filter (per biquad) 1 6.0 ns matrix multiply (pipelined) [33] [31] [44] [41] 13.5 ns 23.9 ns divide (y/x) 10.5 ns inverse square root 16.3 ns table 2. adsp-2136x family features feature adsp-21362 adsp-21363 adsp-21364 adsp-21365 adsp-21366 ram rom 3m bit 4m bit 3m bit 4m bit 3m bit 4m bit 3m bit 4m bit 3m bit 4m bit audio decoders in rom 1 no no no yes yes pulse-width modulation yes yes yes yes yes s/pdif yes no yes yes yes dtcp 2 yes no no yes no src snr performance C128 db no src C140 db C128 db C128 db 1 audio decoding algorithms include pcm, do lby digital ex, dolby pro logic iix, dts 96 /24, neo:6, dts es, mpeg-2 aac, mp3, and fu nctions like bass management, delay, speaker equalization, graphic eq ualization, and more. de coder/post-processor algorithm combin ation support vari es depending upo n the chip version and the system configurations. please visit www.an alog.com for complete information. 2 the adsp-21362 and adsp-21365 processors provide the digital tran smission content protection protocol, a proprietary security p rotocol. contact your analog devices sales office for more information.
rev. g | page 4 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 sharc family core architecture the adsp-2136x is code-compatibl e at the assembly level with the adsp-2126x, adsp-21160, an d adsp-21161, and with the first generation adsp-2106x sharc processors. the adsp-2136x shares architectural features with the adsp-2126x and adsp-2116x simd sharc processors, as shown in figure 2 and detailed in the following sections. simd computational engine the processor contains two comp utational processing elements that operate as a single-instruction, multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey can be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math intensive signal processing algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel alu and multiplier operations occur in both processing elements. these computation units support ieee 32-bit, single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. figure 2. sharc co re block diagram s simd core cache interrupt 5 stage program sequencer pm address 32 dm address 32 dm data 64 pm data 64 dag1 16x32 mrf 80-bit alu multiplier shifter rf rx/fx pex 16x40-bit jtag dmd/pmd 64 pm data 48 astatx stykx astaty styky timer rf sx/sfx pey 16x40-bit mrb 80-bit msb 80-bit msf 80-bit flag system i/f ustat 4x32-bit px 64-bit dag2 16x32 alu multiplier shifter data swap pm address 24
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 5 of 56 | march 2011 data register file each processing element contains a general-purpose data regis- ter file. the register files transf er data between the computation units and the data buses, and st ore intermediate results. these 10-port, 32-register (16 primary, 16 secondary) files, combined with the adsp-2136x enhanced harvard archit ecture, allow unconstrained data flow between computation units and inter- nal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. context switch many of the processors register s have secondary registers that can be activated during interrupt servicing for a fast context switch. the data regist ers in the register file, the dag registers, and the multiplier resu lt register all have secondary registers. the primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. universal registers the universal registers are ge neral purpose registers. the ustat (4) registers allow easy bit manipulations (set, clear, toggle, test, xor) for all system registers (control/status) of the core. the data bus exchange register (px) permits data to be passed between the 64-bit pm data bus and the 64-bit dm data bus, or between the 40-bit register file and the pm/dm data bus. these registers contain hardware to handle the data width difference. timer a core timer that can generate periodic software interrupts. the core timer can be configured to use flag3 as a timer expired signal. single-cycle fetch of instruction and four operands the processor features an enhanced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 2 ). with the its separate program and data memory buses and on-chip instruction ca che, the processor can simulta- neously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the processor includes an on -chip instruction cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators wi th zero-overhead hardware circular buffer support the processors two data addre ss generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filt ers and fourier transforms. the two dags contai n sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automati cally handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations for concise prog ramming. for example, the processor can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. on-chip memory the processor contains 3m bits of internal sram and 4m bits of internal rom. each block can be configured for different combinations of code and data storage (see table 3 ). each memory block supports single-c ycle, independent accesses by the core processor and i/o proc essor. the processors memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the i/o processor, in a single cycle. the sram can be configured as a maximum of 96k words of 32-bit data, 192k words of 16-bi t data, 64k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 3m bits. all of the me mory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectiv ely doubles the amount of data that can be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. while each memory block can store combi- nations of code and data, accesse s are most efficient when one block stores data using the dm bus for transfers, and the other block stores instructions an d data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. on-chip memory bandwidth the internal memory architecture allows three accesses at the same time to any of the four blocks, assuming no block con- flicts. the total bandwidth is gained with dmd and pmd buses (2 64-bits, core clk) and the iod bus (32-bit, pclk). rom-based security the processor has a rom security feature that provides hard- ware support for securing user software code by preventing unauthorized reading from the in ternal code. when using this feature, the processor does not boot-load any external code, exe- cuting exclusively from inte rnal rom. additionally, the processor is not freely accessible via the jtag port. instead, a unique 64-bit key, which must be scanned in through the jtag
rev. g | page 6 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 or test access port, will be assign ed to each customer. the device will ignore a wrong key. emulation features and external boot modes are only available after the correct key is scanned. family peripheral architecture the adsp-2136x family contains a rich set of peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications, military, test equip- ment, 3d graphics, speech recognition, monitor control, imaging, and other applications. parallel port the parallel port provides inte rfaces to sram and peripheral devices. the multiplexed address and data pins (ad15C0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of ad dress. in either mode, 8-bit or 16-bit, the maximum data transfer rate is 55 mbps. dma transfers are used to move data to and from internal memory. access to the core is also facilitated through the paral- lel port register read/write functions. the rd , wr , and ale (address latch enable) pins are the control pins for the parallel port. serial peripheral (compatible) interface the processors contain two serial peripheral interface ports (spis). the spi is an industry-s tandard synchronous serial link, enabling the processors spi-co mpatible port to communicate with other spi-compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, su pporting both master and slave modes and can operate at a maximum baud rate of f pclk /4. the spi port can operate in a multimaster environment by interfacing with up to four othe r spi-compatible devices, either acting as a master or slav e device. the adsp-2136x spi- compatible peripheral implemen tation also features program- mable baud rate, clock phase, and polarities. the spi- compatible port uses open drai n drivers to support a multimas- ter configuration and to avoid data contention. pulse-width modulation the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. the pwm module is a flexible , programmable, pwm waveform generator that can be programm ed to generate the required switching patterns for various appl ications related to motor and engine control or audio power control. the pwm generator can table 3. adsp-2136x internal memory space iop registers 0x0000 0000C0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom 0x0004 0000C0x0004 7fff block 0 rom 0x0008 0000C0x0008 aaa9 block 0 rom 0x0008 0000C0x0008 ffff block 0 rom 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 bfff reserved 0x0009 0000C0x0009 7fff reserved 0x0012 0000C0x0012 ffff block 0 sram 0x0004 c000C0x0004 ffff block 0 sram 0x0009 0000C0x0009 5554 block 0 sram 0x0009 8000C0x0009 ffff block 0 sram 0x0013 0000C0x0013 ffff block 1 rom 0x0005 0000C0x0005 7fff block 1 rom 0x000a 0000C0x000a aaa9 block 1 rom 0x000a 0000C0x000a ffff block 1 rom 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 bfff reserved 0x000b 0000C0x000b 7fff reserved 0x0016 0000C0x0016 ffff block 1 sram 0x0005 c000C0x0005 ffff block 1 sram 0x000b 0000C0x000b 5554 block 1 sram 0x000b 8000C0x000b ffff block 1 sram 0x0017 0000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 1fff block 2 sram 0x000c 0000C0x000c 2aa9 block 2 sram 0x000c 0000C0x000c 3fff block 2 sram 0x0018 0000C0x0018 7fff reserved 0x0006 2000C0x0006 ffff reserved 0x000c 4000C0x000d ffff reserved 0x0018 8000C0x001b ffff block 3 sram 0x0007 0000C0x0007 1fff block 3 sram 0x000e 0000C0x000e 2aa9 block 3 sram 0x000e 0000C0x000e 3fff block 3 sram 0x001c 0000C0x001c 7fff reserved 0x0007 2000C0x0007 ffff reserved 0x000e 4000C0x000f ffff reserved 0x001c 8000C0x001f ffff reserved 0x0020 0000C0xffff ffff
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 7 of 56 | march 2011 generate either center-aligned or edge-align ed pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode, the duty cycle values are prog rammable only once per pwm period. this results in pwm pa tterns that are symmetrical about the midpoint of the pw m period. in double update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce lower harmonic distortion in 3-phase pwm inverters. digital audio interface (dai) the digital audio interface (dai) provides the ability to connect various peripherals to any of the dsps dai pins (dai_p20C1). programs make these connections using the signal routing unit (sru, shown in figure 1 ). the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. this allows easy use of the dai-associated peripherals for a wider variety of applications by using a larger set of algorithms than is possible with nonconfig- urable signal paths. the dai includes six serial port s, an s/pdif receiver/transmit- ter, a dtcp cipher, a precisio n clock generator (pcg), eight channels of asynchronous sample rate converters, an input data port (idp), an spi port, six flag outputs and six flag inputs, and three timers. the idp provides an additional input path to the adsp-2136x core, configurable as either eight channels of i 2 s serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisitio n port. each data channel has its own dma channel that is independent from the processors serial ports. serial ports the processor features six synchr onous serial ports that provide an inexpensive interface to a wide variety of digital and mixed- signal peripheral devices such as analog devices ad183x fam- ily of audio codecs, adcs, and dacs. the serial ports are made up of two data lines, a clock, and a frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data wh en all six sports are enabled, or six full duplex tdm stream s of 128 channels per frame. serial port data can be automa tically transferred to and from on-chip memory via dedicated dma channels. each of the serial ports can work in conjunct ion with another serial port to provide tdm support. one sport provides two transmit sig- nals while the other sport prov ides the two receive signals. the frame sync and clock are shared. serial ports operate in four modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ? left-justified sample pair mode s/pdif-compatible digital audio receiver/transmitter the s/pdif transmitter has no separate dma channels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16, 18, 20, or 24 bits. the serial data, clock, and fram e sync inputs to the s/pdif transmitter are routed through th e signal routing unit (sru). they can come from a variety of sources such as the sports, external pins, the precision clock generators (pcgs), or the sample rate converters (src) and are controlled by the sru control registers. digital transmission content protection (dtcp) the dtcp specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the ieee 1394 standard. only legitimate entertainment content delivered to a source device via another approved copy protection syst em (such as the dvd content scrambling system) is protected by this copy prot ection system. this feature is available on the adsp-21362 and adsp-21365 processors only. li censing through dtla is required for these products. visit www.dtcp.com for more information. memory-to-memory (mtm) if the dtcp module is not used, the memory-to-memory dma module allows internal memory copies for a standard dma. synchronous/asynchronous sample rate converter (src) the sample rate converter (src) contains four src blocks and is the same core as that us ed in the ad1896 192 khz stereo asynchronous sample rate conver ter and provides up to 140 db snr. the src block is used to perform synchronous or asynchronous sample rate conver sion across independent stereo channels, without using internal processor resources. the four src blocks can also be configur ed to operate together to con- vert multichannel audio data without phase mismatches. finally, the src is used to clean up audio data from jittery clock sources such as the s/pdif receiver. the s/pdif and src are not available on the adsp-21363 models. input data port (idp) the idp provides up to eight se rial input channelseach with its own clock, frame sync, and data inputs. the eight channels are automatically multiplexed into a single 32-bit by eight-deep fifo. data is always formatted as a 64-bit frame and divided into two 32-bit words. the serial protocol is designed to receive
rev. g | page 8 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 audio channels in i2s, left-justi fied sample pair , or right-justi- fied mode. one frame sync cycle indicates one 64-bit left/right pair, but data is sent to the fifo as 32-bit words (that is, one- half of a frame at a time). the processor supports 24- and 32-bit i 2 s, 24- and 32-bit left-justifi ed, and 24-, 20-, 18- and 16-bit right-justified formats. precision clock generator (pcg) the precision clock generators (p cg) consist of two units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. the units, a and b, are identi- cal in functionality and operate independently of each other. the two signals generated by each unit are normally used as a serial bit clock/frame sync pair. peripheral timers the following three general-purpose timers can generate peri- odic interrupts and be independ ently set to operate in one of three modes: ? pulse waveform generation mode ? pulse width count/capture mode ? external event watchdog mode each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configu- ration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register . a single control and status register enables or disables a ll three general-purpose timers independently. i/o processor features the processors i/o provides ma ny channels of dma and con- trols the extensive set of peripherals described in the previous sections. dma controller the processors on-chip dma cont rollers allow data transfers without processor intervention . the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while th e core is simultaneously exe- cuting its program instructio ns. dma transfers can occur between the processors internal me mory and its serial ports, the spi-compatible (serial peripher al interface) ports, the idp (input data port), the parallel da ta acquisition port (pdap), or the parallel port (pp). see table 4 . system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of the proc essor boots at sy stem power-up from an 8-bit eprom via the parallel port, an spi master, an spi slave, or an internal boot. booting is determined by the boot configuration (boot_cfg1C0) pins in table 5 . selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin executing from rom. phase-locked loop the processors use an on-chip ph ase-locked loop (pll) to gen- erate the internal clock for the core. on power-up, the clk_cfg1C0 pins are used to se lect ratios of 32:1, 16:1, and 6:1. after booting, numerous ot her ratios can be selected via software control. the ratios are made up of soft ware configurable numerator val- ues from 1 to 64 and software conf igurable divisor values of 1, 2, 4, and 8. power supplies the processor has a separate po wer supply connection for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.2 v requirement for k, b, an d y grade models, and the 1.0 v requirement for y models. (for information on the temperature ranges offered for this product, see operating conditions on page 14 , package information on page 15 , and ordering guide on page 54 .) the external supply must meet the 3.3 v require- ment. all external supply pins must be connected to the same power supply. note that the analog supply pin (a vdd ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the a vdd pin. place the filter components as close as possible to the a vdd /a vss pins. for an example circuit, see figure 3 . (a recommended ferrite chip is the murata blm18ag102sn1d.) to reduce noise coupling, the pc b should use a parallel pair of power and ground planes for v ddint and gnd. use wide traces to connect the bypass capacitors to the analog power (a vdd ) and ground (a vss ) pins. note that the a vdd and a vss pins specified in figure 3 are inputs to the processor and not the ana- log ground plane on the boardthe a vss pin should connect directly to digital ground (gnd) at the chip. table 4. dma channels peripheral adsp-2136x sports 12 idp/pdap 8 spi 2 mtm/dtcp 2 parallel port 1 total dma channels 25 table 5. boot mode selection boot_cfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 parallel port boot via eprom 11 no booting occurs. processor executes from internal rom after reset.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 9 of 56 | march 2011 target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test a ccess port of the processor to monitor and control the target board processor during emula- tion. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces- sor stacks. the processors jtag interface ensures that the emulator does not affect targ et system load ing or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, refer to the appropriate emulator users guide. development tools the processor is supported with a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and visualdsp++ ? ? devel- opment environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-2136x processors. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy-to-use assembler (based on an algebraic syn- tax), an archiver (librarian/libra ry builder), a linker, a loader, a cycle-accurate instru ction-level si mulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathemati- cal functions. a key point fo r these tools is c/c++ code efficiency. the compiler has been developed for efficient trans- lation of c/c++ code to dsp assembly. the sharc has architectural features that impr ove the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and efficiently. by using the profil er, the programmer can focus on those areas in the program that impact performance and take corrective action. through debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ integrated de velopment and debugging envi- ronment (idde) lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all of the sharc develop- ment tools, including the colo r syntax highli ghting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk is designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but can also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk-based objects, and vi sualizing the system state, when debugging an application that uses the vdk. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. figure 3. analog power (a vdd ) filter circuit ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc. high-z ferrite bead chip locate all components close to a vdd and a vss pins a vdd a vss 100nf 10nf 1nf adsp-213xx v ddint
rev. g | page 10 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 the expert linker is fully compatible with the existing linker def- inition file (ldf), allowing the developer to move between the graphical and text ual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc processor pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supp lied an ieee 1149.1 jtag test access port (tap) on each jtag processor. nonintrusive in- circuit emulation is assured by the use of the processors jtag interface. (the emulator does not affect target system loading or timing.) the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, refer to the analog devices jtag emulation technical reference (ee-68) on the analog devices website, www.ana- log.com . (perform a site search on ee-68.) this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? ? evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping applic ations with analog devices processors, platforms, and softwa re tools. each ez-kit lite platform includes an evaluation board along with an evaluation suite of the visualdsp++ development and debugging environ- ment with the c/c++ compiler, assembler, and linker. also included are sample application programs, a power supply, and a usb cable. all evaluation vers ions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-k it lite board connects the board to the usb port of th e users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a stand- alone unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high speed, non- intrusive emulation. additional information this data sheet provides a general overview of the processors architecture and functionality. for detailed informa- tion on the adsp-2136x fami ly core architecture and instruction set, refer to the adsp-2136x sharc processor hardware reference and the adsp-2136x sharc processor programming reference . related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the circuits from the lab tm site ( http://www.analog.com/signalchains ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques ? ez-kit lite is a registered trademark of analog devices, inc.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 11 of 56 | march 2011 pin function descriptions the processors pin definitions are listed below. inputs identi- fied as synchronous (s) must m eet timing requirements with respect to clkin (or with respect to tck for tms and tdi). inputs identified as asynchronous (a) can be asserted asynchro- nously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for the following: dai_px, spiclk, miso, mosi, emu , tms, trst , tdi, and ad15C0. note : these pins have pull-up resistors. table 6. pin descriptions pin type state during and after reset function ad15C0 i/o/t (pu) three-state with pull-up enabled parallel port address/data. the adsp-2136x parallel port and its corresponding dma unit output addresses and data for peripher als on these multiplexed pins. the multiplex state is determined by the ale pin. the parall el port can operate in either 8-bit or 16-bit mode. each ad pin has a 22.5 k internal pu ll-up resistor. for details about the ad pin operation, refer to the adsp-2136x sharc proce ssor hardware reference . for 8-bit mode: ale is automatically asserted whenever a change occurs in the upper 16 external address bits, addr23C8; ale is used in conjunction with an external latch to retain the values of the addr23C8. for detailed information on i/o operations and pin multiplexing, refer to the adsp-2136x sharc processor ha rdware reference . rd o (pu) three-state, driven high 1 parallel port read enable. rd is asserted low whenever the processor reads 8-bit or 16- bit data from an external memory device. when ad15C0 are flags, this pin remains deasserted. rd has a 22.5 k internal pull-up resistor. wr o (pu) three-state, driven high 1 parallel port write enable. wr is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. when ad15C0 are flags, this pin remains deasserted. wr has a 22.5 k internal pull-up resistor. ale o (pd) three-state, driven low 1 parallel port address latch enable. ale is asserted whenever the processor drives a new address on the parallel port address pins. on reset, ale is active high. however, it can be reconfigured using software to be active low. when ad15C0 are flags, this pin remains deasserted. ale has a 20 k internal pull-down resistor. flag[0]/irq0 /spi flg[0] i/o flag[0] input flag0/interrupt request0/spi0 slave select. flag[1]/irq1 /spi flg[1] i/o flag[1] input flag1/interrupt request1/spi1 slave select. flag[2]/irq2 /spi flg[2] i/o flag[2] input flag2/interrupt request 2/spi2 slave select . flag[3]/tmrexp/ spiflg[3] i/o flag[3] input flag3/timer expired/spi3 slave select. dai_p20C1 i/o/t (pu) three-state with programmable pull-up digital audio interface pins . these pins provide the physical interface to the sru. the sru configuration registers define the comb ination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. the configuration registers of these peripherals then determine the exact behavior of the pin. any input or output signal present in the sru can be routed to any of these pins. the sru provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and spi to the dai_p20C1 pins. these pins have internal 22.5 k pull-up resistors that are en abled on reset. these pull-ups can be disabled using the dai_pin_pullup register. the following symbols appear in the type column of table 6 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, ( a/d ) = active drive, ( o/d ) = open drain, and t = three-state, ( pd ) = pull-down resistor, ( pu ) = pull-up resistor.
rev. g | page 12 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 spiclk i/o (pu) three-state with pull-up enabled, driven high in spi- master boot mode serial peripheral interface clock signal. driven by the master, this signal controls the rate at which data is transferred. the master can transmit data at a variety of baud rates. spiclk cycles once for each bit transmitted. spiclk is a gated clock active during data transfers, only for the length of the transfer red word. slave devices ignore the serial clock if the slave select input is driven inactive (high). spiclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the sp ictl control register and define the transfer format. spiclk has a 22.5 k internal pull-up resistor. spids i input only serial peripheral interface slave device select. an active low signal used to select the processor as an spi slave device. this input signal behaves like a chip select, and is provided by the master device for the slave devices. in multimaster mode the processors spids signal can be driven by a slave device to signal to the processor (as spi master) that an error has occurred, as some other device is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multimaster error. for a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to v ddext on the master device. for processor to processor spi inter- action, any of the master processors flag pins can be used to drive the spids signal on the spi slave device. mosi i/o (o/d) (pu) three-state with pull-up enabled, driven low in spi- master boot mode spi master out slave in. if the adsp-2136x is configured as a master, the mosi pin becomes a data transmit (output) pin, tran smitting output data. if the processor is configured as a slave, the mosi pin becomes a data receive (input) pin, receiving input data. in an spi interconnection, the data is shifted out from the mosi output pin of the master and shifted into the mosi input(s) of the slave(s). mosi has a 22.5 k internal pull- up resistor. miso i/o (o/d) (pu) three-state with pull-up enabled spi master in slave out. if the adsp-2136x is configured as a master, the miso pin becomes a data receive (input) pin, receiving input data. if the processor is configured as a slave, the miso pin becomes a data tran smit (output) pin, transmitting output data. in an spi interconnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the ma ster. miso has a 22.5 k internal pull-up resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note: only one slave is allowed to transmit data at any given time. to enable broadcast transmission to multiple spi slaves, the proc essors miso pin can be disabled by setting bit 5 (dmiso) of the spictl register equal to 1. clkin i input only local clock in. used in conjunction with xtal. clkin is the adsp-2136x clock input. it configures the adsp-2136x to use either its in ternal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal uncon- nected configures the processors to use the external clock source such as an external clock oscillator. the core is clocked either by the pll output or this clock input depending on the clk_cfg1C0 pin settings. clkin shou ld not be halted, changed, or operated below the specified frequency. xtal o output only 2 crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. clk_cfg1C0 i input only core to clkin ratio control. these pins set the start up cl ock frequency. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. the allowed values are: 00 = 6:1 01 = 32:1 10 = 16:1 11 = reserved. table 6. pin descriptions (continued) pin type state during and after reset function the following symbols appear in the type column of table 6 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, ( a/d ) = active drive, ( o/d ) = open drain, and t = three-state, ( pd ) = pull-down resistor, ( pu ) = pull-up resistor.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 13 of 56 | march 2011 boot_cfg1C0 i input only boot configuration select. this pin is used to select the boot mode for the processor. the boot_cfg pins must be valid before reset is asserted. for a description of the boot mode, refer to the adsp-2136x sharc processor hardware reference . resetout o output only reset out. drives out the core reset signal to an external device. reset i/a input only processor reset. resets the adsp-2136x to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i input only 3 test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the processors. tms i/s (pu) three-state with pull-up enabled test mode select (jtag). used to control the test state machine. tms has a 22.5 k internal pull-up resistor. tdi i/s (pu) three-state with pull-up enabled test data input (jtag). provides serial data for the boundary scan logic. tdi has a 22.5 k internal pull-up resistor. tdo o three-state 4 test data output (jtag). serial scan output of the boundary scan path. trst i/a (pu) three-state with pull-up enabled test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for prope r operation of the adsp-2136x. trst has a 22.5 k internal pull-up resistor. emu o (o/d) (pu) three-state with pull-up enabled emulation status. must be connected to the processors jtag emulators target board connector only. emu has a 22.5 k internal pull-up resistor. v ddint p core power supply. nominally +1.2 v dc for the k, b grade models, and 1.0 v dc for the y grade models, and supplies the processors core. v ddext p i/o power supply. nominally +3.3 v dc. a vdd p analog power supply. nominally +1.2 v dc for the k, b grade models, and 1.0 v dc for the y grade models, and supplies the processor s internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 8. a vss g analog power supply return. gnd g power supply return. 1 rd , wr , and ale are three-stated (and not driven) only when reset is active. 2 output only is a three-state driver wi th its output path always enabled. 3 input only is a three-state driver with both output path and pull-up disabled. 4 three-state is a three-state driver with pull-up disabled. table 6. pin descriptions (continued) pin type state during and after reset function the following symbols appear in the type column of table 6 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, ( a/d ) = active drive, ( o/d ) = open drain, and t = three-state, ( pd ) = pull-down resistor, ( pu ) = pull-up resistor.
rev. g | page 14 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 specifications specifications are subject to change without notice. operating conditions electrical characteristics k grade b grade y grade parameter description min max min max min max unit v ddint internal (core) supply voltage 1.14 1.26 1.14 1.26 0.95 1.05 v a vdd analog (pll) supply voltage 1.14 1.26 1.14 1.26 0.95 1.05 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 3.13 3.47 v v ih 1 1 applies to input and bid irectional pins: ad15C0, flag3C0, dai_px, spiclk, mosi, miso, spids , boot_cfgx, clk_cfgx, reset , tck, tms, tdi, and trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 2.0 v ddext + 0.5 2.0 v ddext + 0.5 v v il 1 low level input voltage @ v ddext = min C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 v v ih_clkin 2 2 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 1.74 v ddext + 0.5 1.74 v ddext + 0.5 v v il_clkin low level input voltage @ v ddext = min C0.5 +1.19 C0.5 +1.19 C0.5 +1.19 v t j 3, 4 3 see adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-2 1366 for information on thermal specifications. 4 see estimating power for the adsp -21362 sharc processors (ee-277) for further information. junction temperature 136-ball csp_bga 0 +110 C40 +125 C40 +125 c t j 3, 4 junction temperature 144-lead lqfp_ep 0 +110 C40 +125 C40 +125 c parameter description test conditions min max unit v oh 1 high level output voltage @ v ddext = min, i oh = C1.0 ma 2 2.4 v v ol 1 low level output voltage @ v ddext = min, i ol = 1.0 ma 2 0.4 v i ih 3, 4 high level input current @ v ddext = max, v in = v ddext max 10 a i il 3 low level input current @ v ddext = max, v in = 0 v 10 a i ilpu 4 low level input current pull-up @ v ddext = max, v in = 0 v 200 a i ozh 5, 6 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 5 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 6 three-state leakage current pull-up @ v ddext = max, v in = 0 v 200 a i dd-intyp 7, 8 supply current (internal) t cclk = min, v ddint = nom 800 ma ia vdd 9 supply current (analog) a vdd = max 10 ma c in 10, 11 input capacitance f in = 1 mhz, t case = 25c, v in = 1.2 v 4.7 pf 1 applies to output and bidir ectional pins: ad15C0, rd , wr , ale, flag3C0, dai_px, spiclk, mosi, miso, emu , tdo, and xtal. 2 see output drive currents on page 44 for typical drive current capabilities. 3 applies to input pins: spids , boot_cfgx, clk_cfgx, tck, reset , and clkin. 4 applies to input pins with 22.5 k internal pull-ups: trst , tms, tdi. 5 applies to three-stateable pins: flag3C0. 6 applies to three-stateable pins with 22.5 k pull-ups: ad15C0, dai_px, spiclk, emu , miso , and mosi . 7 typical internal current data reflec ts nominal operating conditions. 8 see estimating power for the adsp -21362 sharc processors (ee-277) for further information. 9 characterized, but not tested. 10 applies to all signal pins. 11 guaranteed, but not tested.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 15 of 56 | march 2011 package information the information presented in figure 4 provides details about the package branding for the adsp-2136x processor. for a complete listing of pr oduct availability, see ordering guide on page 54 . esd caution maximum power dissipation see estimating power for the adsp-21362 sharc processors (ee-277) for detailed thermal and power information regarding maximum power dissipation. for information on package ther- mal specifications, see thermal characteristics on page 45 . absolute maximum ratings stresses greater than those listed in table 8 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing specifications use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. for voltage reference levels, see figure 39 on page 44 under test conditions . switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. core clock requirements the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequency and external (clkin) clock frequency with the clk_cfg1C0 pins. the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an in ternal phase-locked loop (pll, see figure 5 ). this pll-based clocki ng minimizes the skew between the system clock (clkin ) signal and the processors internal clock. voltage controlled oscillator in application designs, the p ll multiplier value should be selected in such a way that the vco frequency never exceeds f vco specified in table 11 . ? the product of clkin and pllm must never exceed 1/2 f vco (max) in table 11 if the input divider is not enabled (indiv = 0). figure 4. typical package brand table 7. package brand information brand key field description t temperature range pp package type z rohs compliant designation cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code tppz-cc s adsp-2136x a #yyww country_of_origin vvvvvv.x n.n esd (e l ectrostatic discharge) sensitive device. charged devi c es and c ir c uit boards c an dis c harge without dete c tion. a l though this produ c t features patented or proprietary prote c tion c ir c uitry, damage may o cc ur on devi c es subje c ted to high energy esd. t herefore, proper esd pre c autions shou l d be taken to avoid performan c e degradation or l oss of fun c tiona l ity. table 8. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.5 v analog (pll) supply voltage (a vdd )C0.3 v to +1.5 v external (i/o) supply voltage (v ddext )C0.3 v to +4.6 v input voltage C0.5 v to +3.8 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65c to +150c junction temperature while biased 125c
rev. g | page 16 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 ? the product of clkin and pllm must never exceed f vco (max) in table 11 if the input divider is enabled (indiv = 1). the vco frequency is calculated as follows: f vco = 2 pllm f input f cclk = (2 pllm f input ) (2 plln ) where: f vco = vco output pllm = multiplier value programm ed in the pmctl register. during reset, the pllm value is derived from the ratio selected using the clk_cfg pins in hardware. plln = 1, 2, 4, 8 based on the plld value programmed on the pmctl register. during reset this value is 1. f input = input frequency to the pll. f input = clkin when the input divider is disabled or f input = clkin 2 when the input divider is enabled note the definitions of the clock periods that are a function of clkin and the appropriate ratio control shown in table 9 . all of the timing specifications fo r the adsp-2136x peripherals are defined in relation to t pclk . refer to the peripheral specific sec- tion for each peripherals timing information. figure 5 shows core to clkin relati onships with external oscil- lator or crystal. the shaded di vider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (pmctl). for more information, refer to the adsp-2136x sharc processor hardware reference . table 9. clock periods timing requirements description t ck clkin clock period t cclk processor core clock period t pclk peripheral clock period = 2 t cclk figure 5. core clock and system clock relationship to clkin clkout (test only)* loop filter pll f vco (2 pllm) vco pll divider pmctl (plld) f vco f cclk clk_cfgx/ pmctl (2 pllm) clkin pclk xtal clkin divider resetout delay of 4096 clkin cycles reset buf buf pmctl (indiv) pmctl (pllbp) bypass mux pin mux divide by 2 resetout pmctl (clkouten) cclk corerst *clkout (test only) frequency is the same as f input. this signal is not specified or supported for any design. f input
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 17 of 56 | march 2011 power-up sequencing the timing requirements for pr ocessor startup are given in table 10 . note that during power-up, when the v ddint power supply comes up after v ddext , a leakage current of the order of three-state leakage current pull- up, pull-down, may be observed on any pin, even if that is an input only (for example the reset pin) until the v ddint rail has powered up. table 10. power-up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 3, 4 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 v rail s and 3.3 v rails. voltage ramp rates can vary fr om microseconds to hundreds of milliseconds, depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case start-up timing of crystal oscillators. refer to your crystal oscillato r manufacturers data sh eet for start-up time. assume a 25 ms maximum oscillator start-up ti me if using the xtal pin and internal osci llator circuit in conjunction with an ex ternal crystal. 3 applies after the power-up sequence is complete. subseque nt resets require a minimum of 4 clkin cycles for reset to be held low to properly initialize and propagate default states at all i/o pins. 4 the 4096 cycle count depends on t srst specification in table 12 . if setup time is not met, 1 additional clkin cycle can be added to the core reset ti me, resulting in 4097 cycles maximum. figure 6. power-up sequencing t rstvdd t clkvdd t clkrst t corerst t pllrst v ddext v ddint clkin clk_cfg1C0 reset resetout t ivddevdd
rev. g | page 18 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 clock input clock signals the processor can use an external clock or a crystal. refer to the clkin pin description in table 6 on page 11 . the user applica- tion program can configure the processor to use its internal clock generator by connecting th e necessary components to the clkin and xtal pins. figure 8 shows the component connec- tions used for a fundamental fr equency crystal operating in parallel mode. note that the clock rate is achieved using a 16.67 mhz crystal and a pll multiplier ratio 16:1. (cclk:clkin achieves a clock speed of 266.72 mhz.) to achieve the full core clock rate, pro- grams need to configure th e multiplier bits in the pmctl register. table 11. clock input parameter 200 mhz 1 1 applies to all 20 0 mhz models. see ordering guide on page 54 . 333 mhz 2 2 applies to all 33 3 mhz models. see ordering guide on page 54 . unit min max min max timing requirements t ck clkin period 30 3 3 applies only for clk_cfg1C0 = 00 and default va lues for pll control bits in the pmctl register. 100 18 1 100 ns t ckl clkin width low 12.5 1 7.5 1 ns t ckh clkin width high 12.5 1 7.5 1 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 3 ns t cclk 4 4 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 5.0 1 10 3.0 1 10 ns t vco 5 5 see figure 5 on page 16 for vco diagram. vco frequency 200 600 200 800 mhz t ckj 6,7 6 actual input jitter should be combined with ac specifications for acc urate timing analysis. 7 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 C250 +250 ps figure 7. clock input clkin t ck t ckl t ckh t ckj f 8. rmmn ct f nmnt m cyt optn c1 22pf y1 r1 1m * xtal clkin c2 22pf 24.576mhz r2 * adsp-2136x r2 should be chosen to limit crystal drive power. refer to crystal manufacturers specifications. *typical values 47
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 19 of 56 | march 2011 reset interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts. table 12. reset parameter min unit timing requirements t wrst 1 reset pulse width low 4 t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequen ce is complete. at power-up, th e processors internal phase-locked loop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 9. reset clkin reset t srst t wrst table 13. interrupts parameter min unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 10. interrupts dai_p20C1 flag2C0 (irq2C0) t ipw
rev. g | page 20 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 core timer the following timing specification applies to flag3 when it is configured as the core timer (tmrexp pin). timer pwm_out cycle timing the following timing specification applies to timer0, timer1, and timer2 in pwm_out (pulse-width modulation) mode. timer signals are routed to the dai_p20C1 pins through the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 14. core timer parameter min unit switching characteristic t wctim tmrexp pulse width 2 t pclk C 1 ns figure 11. core timer flag3 (tmrexp) t wctim table 15. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1 2(2 31 C 1) t pclk ns figure 12. timer pwm_out timing dai_p20C1 (timer2C0) t pwmo
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 21 of 56 | march 2011 timer wdth_cap timing the following timing specification applies to timer0, timer1, and timer2 in wdth_cap (pul se width count and capture) mode. timer signals are routed to the dai_p20C1 pins through the sru. therefore, the timing specification provided below are valid at the dai_p20C1 pins. dai pin to pin direct routing for direct pin connections only (for example, dai_pb01_i to dai_pb02_o). table 16. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2(2 31 C 1) t pclk ns figure 13. timer width capture timing dai_p20C1 (timer2C0) t pwi table 17. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 10 ns figure 14. dai pin to pin direct routing dai_pn dai_pm t dpio
rev. g | page 22 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 through dai_p20). table 18. precision clock generator (direct pin routing) k and b grade y grade parameter min max max unit timing requirement s t pcgip input clock period t pclk 4 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3 ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + (2.5 t pcgip ) 10 + (2.5 t pcgip ) 12 + (2.5 t pcgip )ns t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip ) 12 + ((2.5 + d C ph) t pcgip )ns t pcgop 1 output clock period 2 t pcgip C 1 ns d = fsxdiv, ph = fsxphase. for more information, refer to the adsp-2136x sharc processor hardware reference , precision clock gener- ators chapter. 1 in normal mode, t pcgop (min) = 2 t pcgip . figure 15. precision clock generator (direct pin routing) dai_pn pcg_trigx_i dai_pm pcg_extx_i (clkin) dai_py pcg_clkx_o dai_pz pcg_fsx_o t dtrigfs t dtrigclk t dpcgio t strig t htrig t pcgop t dpcgio t pcgip
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 23 of 56 | march 2011 flags the timing specifications provided below apply to the flag3C0 and dai_p20C1 pins, the parallel port, and the serial peripheral interface (spi). see table 6 on page 11 for more information on flag use. table 19. flags parameter min unit timing requirement t fipw flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t pclk C 1 ns figure 16. flags dai_p20C1 (flag3C0 in ) (ad15C0) dai_p20C1 (flag3C0 out ) (ad15C0) t fopw t fipw
rev. g | page 24 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 memory readparallel port use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) when the processor is accessing external memory space. table 20. 8-bit memory read cycle parameter k and b grade y grade min max min max unit timing requirements t drs ad7C0 data setup before rd high 3.3 4.5 ns t drh ad7C0 data hold after rd high 0 0 ns t dad ad15C8 address to ad7C0 data valid d + t pclk C 5.0 d + t pclk C 5.0 ns switching characteristics t alew ale pulse width 2 t pclk C 2.0 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.5 t pclk C 2.5 ns t rrh delay between rd rising edge to next falling edge h + t pclk C 1.4 h + t pclk C 1.4 ns t alerw ale deasserted to read asserted 2 t pclk C 3.8 2 t pclk C 3.8 ns t rwale read deasserted to ale asserted f + h + 0.5 f + h + 0.5 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 2.3 t pclk C 2.3 ns t alehz 1 ale deasserted to ad7C0 address in high-z t pclk t pclk + 3.0 t pclk t pclk + 3.8 ns t rw rd pulse width d C 2.0 d C 2.0 ns t rddrv ad7C0 ale address drive after read high f + h + t pclk C 2.3 f + h + t pclk C 2.3 ns t adrh ad15C8 address hold after rd high h h ns t dawh ad15C8 address to rd high d + t pclk C 4.0 d + t pclk C 4.0 ns d = (the value set by the ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 17. read cycle for 8-bit memory timing ale rd wr ad15C8 ad7C0 t alew t alerw t rwale t rw t rrh t rddrv t dawh t adas t adah valid address valid address valid address valid address valid address valid address valid data valid data t adrh t dad t drs t drh t alehz note: memory reads always occur in groups of four between ale cycles. this figure shows only two memory reads to provide the necessary timing information.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 25 of 56 | march 2011 table 21. 16-bit memory read cycle parameter k and b grade y grade min max min max unit timing requirements t drs ad15C0 data setup before rd high 3.3 4.5 ns t drh ad15C0 data hold after rd high 0 0 ns switching characteristics t alew ale pulse width 2 t pclk C 2.0 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.5 t pclk C 2.5 ns t alerw ale deasserted to read asserted 2 t pclk C 3.8 2 t pclk C 3.8 ns t rrh 2 delay between rd rising edge to next falling edge h + t pclk C 1.4 h + t pclk C 1.4 ns t rwale read deasserted to ale asserted f + h + 0.5 f + h + 0.5 ns t rddrv ale address drive after read high f + h + t pclk C 2.3 f + h + t pclk C 2.3 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 2.3 t pclk C 2.3 ns t alehz1 ale deasserted to address/data15C0 in high-z t pclk t pclk + 3.0 t pclk t pclk + 3.8 ns t rw rd pulse width d C 2.0 d C 2.0 ns d = (the value set by the ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. 2 this parameter is only avai lable when in empp = 0 mode. figure 18. read cycle for 16-bit memory timing t rwale t rddrv valid address valid data valid data valid address ale rd wr ad15C0 t adas t adah t alehz t drs t drh t alew t alerw t rw t rrh note: for 16-bit memory reads, when empp 0, only one rd pulse occurs between ale cycles. when empp = 0, multiple rd pulses occur between ale cycles. for complete information, see the adsp-2136x sharc processor hardware reference.
rev. g | page 26 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 memory writeparallel port use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) when the processor is accessing external memory space. table 22. 8-bit memory write cycle parameter k and b grade y grade min min unit switching characteristics t alew ale pulse width 2 t pclk C 2.0 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.8 t pclk C 2.8 ns t alerw ale deasserted to write asserted 2 t pclk C 3.8 2 t pclk C 3.8 ns t rwale write deasserted to ale asserted h + 0.5 h + 0.5 ns t wrh delay between wr rising edge to next wr falling edge f + h + t pclk C 2.3 f + h + t pclk C 2.3 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 0.5 t pclk C 0.5 ns t ww wr pulse width d C f C 2.0 d C f C 2.0 ns t adwl ad15C8 address to wr low t pclk C 2.8 t pclk C 3.5 ns t adwh ad15C8 address hold after wr high h h ns t dws ad7C0 data setup before wr high d C f + t pclk C 4.0 d C f + t pclk C 4.0 ns t dwh ad7C0 data hold after wr high h h ns t dawh ad15C8 address to wr high d C f + t pclk C 4.0 d C f + t pclk C 4.0 ns d = (the value set by the ppdur bits (5C1) in the ppctl register) t pclk . h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) . if flash_mode is set, d must be 9 t pclk . 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 19. write cycle for 8-bit memory timing ad15 - 8 valid address valid address t adas ad7 - 0 ale rd wr t adah t adwh t adwl valid data t dawh t wrh t rwale valid address valid data t alew t alerw t ww t dws t dwh valid address note: memory writes always occur in groups of four between ale cycles. this figure shows only two memory writes to provide the necessary timing information.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 27 of 56 | march 2011 table 23. 16-bit memory write cycle parameter k and b grade y grade min min unit switching characteristics t alew ale pulse width 2 t pclk C 2.0 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.5 t pclk C 2.5 ns t alerw ale deasserted to write asserted 2 t pclk C 3.8 2 t pclk C 3.8 ns t rwale write deasserted to ale asserted h + 0.5 h + 0.5 ns t wrh 2 delay between wr rising edge to next wr falling edge f + h + t pclk C 2.3 f + h + t pclk C 2.3 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 2.3 t pclk C 2.3 ns t ww wr pulse width d C f C 2.0 d C f C 2.0 ns t dws ad15C0 data setup before wr high d C f + t pclk C 4.0 d C f + t pclk C 4.0 ns t dwh ad15C0 data hold after wr high h h ns d = (the value set by the ppdur bits (5C1) in the ppctl register) t pclk . h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) . if flash_mode is set, d must be 9 t pclk . t pclk = (peripheral) clock period = 2 t cclk 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. 2 this parameter is only avai lable when in empp = 0 mode. figure 20. write cycle for 16-bit memory timing t rwale t rddrv valid address valid data valid data valid address ale rd wr ad15C0 t adas t adah t alehz t drs t drh t alew t alerw t rw t rrh note: for 16-bit memory reads, when empp 0, only one rd pulse occurs between ale cycles. when empp = 0, multiple rd pulses occur between ale cycles. for complete information, see the adsp-2136x sharc processor hardware reference.
rev. g | page 28 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (fs) delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (sclk) width. serial port signals are routed to the dai_p20C1 pins using the sru. therefore, the timing spec ifications provided below are valid at the dai_p20C1 pins. table 24. serial portsexternal clock k and b grade y grade parameter min max max unit timing requirements t sfse 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t hfse 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 2.5 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width (t pclk 4) 2 C 0.5 ns t sclk sclk period t pclk 4 ns switching characteristics t dfse 2 frame sync delay after sclk (internally generated frame sync in either transmit or receive mode) 9.5 11 ns t hofse 2 frame sync hold after sclk (internally generated frame sync in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 9.5 11 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 25. serial portsinternal clock k and b grade y grade parameter min max max unit timing requirements t sfsi 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 7 ns t hfsi 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 frame sync delay after sclk (internally generated frame sync in transmit mode) 3 3.5 ns t hofsi 2 frame sync hold after sclk (internally generated frame sync in transmit mode) C1.0 ns t dfsir 2 frame sync delay after sclk (internally generated frame sync in receive mode) 8 9.5 ns t hofsir 2 frame sync hold after sclk (internally generated frame sync in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3 4.0 ns t hdti 2 transmit data hold after sclk C1.0 ns t sclkiw transmit or receive sclk width 2 t pclk C 2 2 t pclk + 2 2 t pclk + 2 ns 1 referenced to the sample edge. 2 referenced to drive edge.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 29 of 56 | march 2011 figure 21. serial ports drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk) t hofsir t hfsi t hdri data receiveinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (sclk) dai_p20C1 (sclk) t hfsi t ddti data transmitinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk) t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk) t hofse t hfse t hdre data receiveexternal clock note: either the rising edge or the falling edge of sclk (external or internal) can be used as the active sampling edge. note: either the rising edge or the falling edge of sclk (external or internal) can be used as the active sampling edge. t sclkiw t dfsir t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw
rev. g | page 30 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 table 26. serial portsexternal late frame sync k and b grade y grade parameter min max max unit switching characteristics t ddtlfse 1 data delay from late external transmit frame sync or external receive fs with mce = 1, mfd = 0 9 10.5 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justifi ed sample pair as well as seri al mode, and mce = 1, mfd = 0. figure 22. external late frame sync drive sample external receive fs with mce = 1, mfd = 0 2nd bit dai_p20C1 (sclk) dai_p20C1 (frame sync) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i drive sample late external transmit fs 2nd bit dai_p20C1 (sclk) dai_p20C1 (frame sync) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i t hfse/i notes: this figure reflects changes made to support left-justified sample pair mode. serial port signals (sclk, fs, data channel a/b) are routed to the dai_p20C1 pins using the sru. the timing specifications provided are valid at the dai_p20C1 pins. the characterized sport ac timings are applicable when internal clocks and frames are looped back from the pin, not routed directly through the sru.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 31 of 56 | march 2011 table 27. serial portsenable and three-state k and b grade y grade parameter min max max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 7 8.5 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. figure 23. enable and three-state drive edge drive edge drive edge t ddtin t ddten t ddtte dai_p20C1 (sclk, int) dai_p20C1 (data channel a/b) dai_p20C1 (sclk, ext) dai_p20C1 (data channel a/b)
rev. g | page 32 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 input data port (idp) the timing requirements for the idp are given in table 28 . idp signals are routed to the dai_p20C1 pins using the sru. there- fore, the timing specifications provided below are valid at the dai_p20C1 pins. table 28. idp parameter min unit timing requirements t sisfs 1 frame sync setup before clock rising edge 3 ns t sihfs 1 frame sync hold after clock rising edge 3 ns t sisd 1 data setup before clock rising edge 3 ns t sihd 1 data hold after clock rising edge 3 ns t idpclkw clock width (t pclk 4) 2 C 1 ns t idpclk clock period t pclk 4 ns 1 the data, clock, and frame sync signals ca n come from any of the dai pins. clock and frame sync can also come via the pcgs or sports. the pcgs input can be either clkin or any of the dai pins. figure 24. idp master timing dai_p20C1 (serial clock) sample edge dai_p20C1 (frame sync) dai_p20C1 (data) t ipdclk t ipdclkw t sisfs t sihfs t sihd t sisd
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 33 of 56 | march 2011 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 29 . pdap is the parallel mode operation of channel 0 of the idp. for details on the operation of the idp, refer to the adsp-2136x sharc proces sor hardware reference , the chapter input data port. note that the most significant 16 bits of external 20-bit pdap data can be provided through either the parallel port ad15C0 or the dai_p20C5 pins. the remainin g 4 bits can only be sourced through dai_p4C1. the timing below is valid at the dai_p20C1 pins or at the ad15C0 pins. table 29. parallel data acquisition port (pdap) parameter min unit timing requirements t spclken 1 pdap_clken setup before pdap_clk sample edge 2.5 ns t hpclken 1 pdap_clken hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 3.0 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 2.5 ns t pdclkw clock width (t pclk 4) 2 C 3 ns t pdclk clock period t pclk 4 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk C 1 ns t pdstrb pdap strobe pulse width 2 t pclk C 1.5 ns 1 data source pins are ad15C0 and dai_p4 C1, or dai pins. source pins for serial clock and frame sync are dai pins. figure 25. pdap timing data dai_p20C1 (pdap_clk) sample edge dai_p20C1 (pdap_clken) dai_p20C1 (pdap_strobe) t pdstrb t pdhldd t pdhd t pdsd t spclken t hpclken t pdclk t pdclkw
rev. g | page 34 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 pulse-width modulation generators sample rate converterserial input port the src input signals are routed from the dai_p20C1 pins using the sru. therefore, the timi ng specifications provided in table 31 are valid at the dai_p20C1 pins. this feature is not available on the adsp-21363 models. table 30. pwm timing 1 parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk ns 1 note that the pwm output signals are shared on the parallel port bus (ad15-0 pins). figure 26. pwm timing pwm outputs t pwmw t pwmp table 31. src, serial input port parameter min unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 3 ns t srchfs 1 frame sync hold after serial clock rising edge 3 ns t srcsd 1 sdata setup before serial clock rising edge 3 ns t srchd 1 sdata hold after serial clock rising edge 3 ns t srcclkw clock width 36 ns t srcclk clock period 80 ns 1 the data, serial clock, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via the pcgs or sports. the pcgs input can be either clkin or any of the dai pins. figure 27. src serial input port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srchd t srcsd
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 35 of 56 | march 2011 sample rate converterserial output port for the serial output port, the fr ame-sync is an input and should meet setup and hold times with re gard to the serial clock on the output port. the serial data output has a hold time and delay specification with regard to serial clock. note that the serial clock rising edge is the sampling edge and the falling edge is the drive edge. table 32. src, serial output port k and b grade y grade parameter min max max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 3 ns t srchfs 1 frame sync hold after serial clock rising edge 3 ns switching characteristics t srctdd 1 transmit data delay after serial clock falling edge 10.5 12.5 ns t srctdh 1 transmit data hold after serial clock falling edge 2 ns 1 the data, serial clock, and frame sync signals can come from a ny of the dai pins. the serial clock and frame sync can also com e via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 28. src serial output port timing dai_p20C1 (serial clock) sample edge dai_p20C1 (frame sync) dai_p20C1 (data) t srcclk t srcclkw t srcsfs t srchfs t srctdd t srctdh
rev. g | page 36 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 s/pdif transmitter serial data input to the s/pdif transmitter can be formatted as left justified, i 2 s, or right justified with word widths of 16-, 18-, 20-, or 24-bits. the following se ctions provide timing for the transmitter. s/pdif transmitter-serial input waveforms figure 29 shows the right-justified mo de. frame sync is high for the left channel and low for the ri ght channel. data is valid on the rising edge of serial clock. the msb is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period , the lsb of the data is right- justified to the next frame sync transition. table 33. s/pdif transmitter right-justified mode parameter nominal unit timing requirement t rjd fs to msb delay in right-justified mode 16-bit word mode 18-bit word mode 20-bit word mode 24-bit word mode 16 14 12 8 sclk sclk sclk sclk figure 29. right-justified mode msb left/right channel lsb lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t rjd
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 37 of 56 | march 2011 figure 30 shows the default i 2 s-justified mode. the frame sync is low for the left channel and high for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to the frame sync transition but with a delay. figure 31 shows the left-justified mo de. the frame sync is high for the left channel and low for th e right channel. data is valid on the rising edge of serial clock. the msb is left-justified to the frame sync transition with no delay. table 34. s/pdif transmitter i 2 s mode parameter nominal unit timing requirement t i2sd fs to msb delay in i 2 s mode 1 sclk figure 30. i 2 s-justified mode msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t i2sd table 35. s/pdif transmitter left-justified mode parameter nominal unit timing requirement t ljd fs to msb delay in left-justified mode 0 sclk figure 31. left-justified mode msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t ljd
rev. g | page 38 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 s/pdif transmitter input data timing the timing requirements for th e s/pdif transmitter are given in table 36 . input signals are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. oversampling clock (txclk) switching characteristics the s/pdif transmitter requires an oversampling clock input. this high frequency clock (txclk) input is divided down to generate the internal biphase clock. table 36. s/pdif transmitter input data timing k grade y grade parameter min max min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 3 3 ns t sihfs 1 frame sync hold after serial clock rising edge 3 3 ns t sisd 1 data setup before serial clock rising edge 3 3 ns t sihd 1 data hold after serial clock rising edge 3 3 ns t sitxclkw transmit clock width 9 9.5 ns t sitxclk transmit clock period 20 20 ns t sisclkw clock width 36 36 ns t sisclk clock period 80 80 ns 1 the serial clock, data and frame sync signals can come from any of the dai pins.the serial clock and frame sync signals can al so come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 32. s/pdif transmitter input timing sample edge dai_p20C1 (txclk) dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (sdata) t sitxclkw t sitxclk t sisclkw t sisclk t sisfs t sihfs t sisd t sihd table 37. oversampling clock (txc lk) switching characteristics parameter max unit frequency for txclk = 384 frame sync o versampling ratio frame sync <= 1/t sitxclk mhz frequency for txclk = 256 frame sync 49.2 mhz frame rate (fs) 192.0 khz
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 39 of 56 | march 2011 s/pdif receiver the following section describes timing as it relates to the s/pdif receiver. this feature is not available on the adsp-21363 processors. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 38. s/pdif receiver output timing (internal digital pll mode) parameter min max unit switching characteristics t dfsi frame sync delay after serial clock 5 ns t hofsi frame sync hold after serial clock C2 ns t ddti transmit data delay after serial clock 5 ns t hdti transmit data hold after serial clock C2 ns t sclkiw 1 transmit serial clock width 38 ns 1 serial clock frequency is 64 fs wher e fs = the frequency of frame sync. figure 33. s/pdif receiver internal digital pll mode timing dai_p20C1 (serial clock) sample edge dai_p20C1 (frame sync) dai_p20C1 (data channel a/b) drive edge t sclkiw t dfsi t hofsi t ddti t hdti
rev. g | page 40 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 spi interfacemaster the processor contains two spi ports. the primary has dedi- cated pins and the secondary is available through the dai. the timing provided in table 39 and table 40 applies to both. table 39. spi interface protocolmaster switching and timing specifications parameter k and b grade y grade min max min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 5.2 6.2 ns t sspidm data input valid to spiclk edge (data input setup time) (spi2) 8.2 9.5 ns t hspidm spiclk last sampling edge to data input not valid 2 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 4 t pclk C 2 ns t ddspidm spiclk edge to data out vali d (data out delay time) 3.0 3.0 ns t ddspidm spiclk edge to data out valid (d ata out delay time) (spi2) 8.0 9.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 4 t pclk C 2 4 t pclk C 2 ns t sdscim flag3C0in (spi device select) low to first spiclk edge 4 t pclk C 2.5 4 t pclk C 3.0 ns t sdscim flag3C0in (spi device select) low to first spiclk edge (spi2) 4 t pclk C 2.5 4 t pclk C 3.0 ns t hdsm last spiclk edge to flag3C0in high 4 t pclk C 2 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 4 t pclk C 1 ns figure 34. spi master timing t spichm t sdscim t spiclm t spiclkm t hdsm t spitdm t spiclm t spichm msb valid lsb valid msb valid lsb lsb msb msb t ddspidm t hspidm t sspidm lsb valid flag3C0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) mosi (output) miso (input) mosi (output) miso (input) cphase = 1 cphase = 0 t hdspidm t hspidm t hspidm t sspidm t sspidm t ddspidm t hdspidm
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 41 of 56 | march 2011 spi interfaceslave table 40. spi interface protocolslave switching and timing specifications k and b grade y grade parameter min max max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t pclk 2 t pclk ns ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 5 5 ns t dsoe 1 spids assertion to data out active (spi2) 0 8 9 ns t dsdhi spids deassertion to data high impedance 0 5 5.5 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 8.6 10 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 11.0 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk 5 t pclk ns 1 the timing for these parameters applies when the spi is routed through the signal ro uting unit. for more information, refer to the adsp-2136x sharc p rocessor hardware reference , serial peripheral interface port chapter.
rev. g | page 42 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 figure 35. spi slave timing t spichs t spicls t spiclks t hds t sdppw t sdsco t spicls t spichs t dsoe t ddspids t ddspids t dsdhi t hdspids t hspids t sspids msb valid lsb valid msb valid t sspids lsb lsb msb msb t dsdhi t ddspids t dsov t hspids t sspids t hdspids lsb valid spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) miso (output) mosi (input) miso (output) mosi (input) cphase = 1 cphase = 0
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 43 of 56 | march 2011 jtag test access port and emulation table 41. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4 t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low t ck 2 + 7 ns 1 system inputs = addr15C0, spids , clk_cfg1C0, reset , boot_cfg1C0, miso, mosi, spiclk, dai_px, and flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, addr15C0, rd , wr , flag3C0, emu , and ale. figure 36. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. g | page 44 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 output drive currents figure 37 shows typical i-v characteri stics for the output driv- ers of the processor. the curv es represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 12 on page 19 through table 41 on page 43 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 38 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 39 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 38 ). figure 42 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 40 , figure 41 , and figure 42 may not be linear outside the ranges shown for typi cal output delay versus load capacitance and typical output rise time (20% to 80%, v = min) versus load capacitance. figure 37. adsp-2136x typical drive figure 38. equivalent device loading for ac measurements (includes all fixtures) figure 39. voltage reference levels for ac measurements s weep (v ddext ) voltage (v) - 20 0 3 .5 0.5 1.5 2.5 0 - 40 - 3 0 20 40 - 10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3 .11v, +125c 3 . 3 v, +25c 3 .47v, - 45c v oh 3 0 10 3 .11v, +125c 3 . 3 v, +25c 3 .47v, - 45c 1.0 2.0 3 .0 to output pin v load 30pf 1.5v input or output 1.5v figure 40. typical output rise/fall time (20% to 80%, v ddext = max) figure 41. typical output rise/fall time (20% to 80%, v ddext = min) load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 fall y = 0.0467x + 1.6 3 2 3 y = 0.045x + 1.524 ri s e load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 ri s e fall y = 0.049x + 1.5105 y=0.04 8 2x + 1.4604
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 45 of 56 | march 2011 thermal characteristics the processor is rated for performance over the temperature range specified in operating conditions on page 14 . table 42 through table 44 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies with jesd51-8. test board and thermal via design comply wi th jedec standards jesd51-9 (bga) and jesd51-5 (lqfp_ep). the junction-to-case mea- surement complies with mil-st d-883. all measurements use a 2s2p jedec test board. industrial applications using the bga package require thermal vias, to an embedded ground plane, in the pcb. refer to jedec standard jesd51-9 for printed ci rcuit board thermal ball land and thermal via design information. industrial applications using the lqfp_ep package require thermal trace squares and thermal vias, to an embedded ground plane, in the pcb. refer to je dec standard jesd51-5 for more information. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature ( c) t t = case temperature ( c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter is the typical value from table 42 through table 44 . p d = power dissipation. see estimating power for the adsp-21362 sharc processors (ee-277) for more information. values of ja are provided for pack age comparison and pcb design considerations. values of jc are provided for package comparison and pcb design considerations when an exposed pad is required. note that the thermal characteristics values provided in table 42 through table 44 are modeled values. figure 42. typical output delay or hold versus load capacitance (at ambient temperature) load capacitance (pf) 0 200 50 100 150 10 8 o u t p u t d e l a y o r h o l d ( n s ) 6 0 4 2 - 2 y=0.04 88 x - 1.592 3 - 4 t j t t jt p d () + = table 42. thermal characteristics for bga (no thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 25.40 c/w jma airflow = 1 m/s 21.90 c/w jma airflow = 2 m/s 20.90 c/w jc 5.07 c/w jt airflow = 0 m/s 0.140 c/w jmt airflow = 1 m/s 0.330 c/w jmt airflow = 2 m/s 0.410 c/w table 43. thermal characteristics for bga (thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 23.40 c/w jma airflow = 1 m/s 20.00 c/w jma airflow = 2 m/s 19.20 c/w jc 5.00 c/w jt airflow = 0 m/s 0.130 c/w jmt airflow = 1 m/s 0.300 c/w jmt airflow = 2 m/s 0.360 c/w table 44. thermal characteristics for lqfp_ep (with exposed pad soldered to pcb) parameter condition typical unit ja airflow = 0 m/s 16.80 c/w jma airflow = 1 m/s 14.20 c/w jma airflow = 2 m/s 13.50 c/w jc 7.25 c/w jt airflow = 0 m/s 0.51 c/w jmt airflow = 1 m/s 0.72 c/w jmt airflow = 2 m/s 0.80 c/w
rev. g | page 46 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 144-lead lqfp_ep pin configurations the following table shows the pr ocessors pin names and, when applicable, their default function after reset in parentheses. table 45. lqfp_ep pin assignments pin name pin no. pin name pin no. pin name pin no. pin name pin no. v ddint 1v ddint 37 v ddext 73 gnd 109 clk_cfg0 2 gnd 38 gnd 74 v ddint 110 clk_cfg1 3 rd 39 v ddint 75 gnd 111 boot_cfg0 4 ale 40 gnd 76 v ddint 112 boot_cfg1 5 ad15 41 dai_p10 (sd2b) 77 gnd 113 gnd 6 ad14 42 dai_p11 (sd3a) 78 v ddint 114 v ddext 7 ad13 43 dai_p12 (sd3b) 79 gnd 115 gnd 8 gnd 44 dai_p13 (sclk3) 80 v ddext 116 v ddint 9v ddext 45 dai_p14 (sfs3) 81 gnd 117 gnd 10 ad12 46 dai_p15 (sd4a) 82 v ddint 118 v ddint 11 v ddint 47 v ddint 83 gnd 119 gnd 12 gnd 48 gnd 84 v ddint 120 v ddint 13 ad11 49 gnd 85 reset 121 gnd 14 ad10 50 dai_p16 (sd4b) 86 spids 122 flag0 15 ad9 51 dai_p17 (sd5a) 87 gnd 123 flag1 16 ad8 52 dai_p18 (sd5b) 88 v ddint 124 ad7 17 dai_p1 (sd0a) 53 dai_p19 (sclk5) 89 spiclk 125 gnd 18 v ddint 54 v ddint 90 miso 126 v ddint 19 gnd 55 gnd 91 mosi 127 gnd 20 dai_p2 (sd0b) 56 gnd 92 gnd 128 v ddext 21 dai_p3 (sclk0) 57 v ddext 93 v ddint 129 gnd 22 gnd 58 dai_p20 (sfs5) 94 v ddext 130 v ddint 23 v ddext 59 gnd 95 a vdd 131 ad6 24 v ddint 60 v ddint 96 a vss 132 ad5 25 gnd 61 flag2 97 gnd 133 ad4 26 dai_p4 (sfs0) 62 flag3 98 resetout 134 v ddint 27 dai_p5 (sd1a) 63 v ddint 99 emu 135 gnd 28 dai_p6 (sd1b) 64 gnd 100 tdo 136 ad3 29 dai_p7 (sclk1) 65 v ddint 101 tdi 137 ad2 30 v ddint 66 gnd 102 trst 138 v ddext 31 gnd 67 v ddint 103 tck 139 gnd 32 v ddint 68 gnd 104 tms 140 ad1 33 gnd 69 v ddint 105 gnd 141 ad0 34 dai_p8 (sfs1) 70 gnd 106 clkin 142 wr 35 dai_p9 (sd2a) 71 v ddint 107 xtal 143 v ddint 36 v ddint 72 v ddint 108 v ddext 144 gnd 145* *the epad is electrically connected to gnd inside the chip (see figure 43 and figure 44 ), therefore connecting the pad to gnd is optional. for better thermal performance the epad should be soldered to the board and thermally connected to the gnd plane with vias.
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 47 of 56 | march 2011 figure 43 shows the top view of th e 144-lead lqfp_ep pin con- figuration. figure 44 shows the bottom view of the 144-lead lqfp_ep lead configuration. figure 43. 144-lead lqfp_ep lead configuration (top view) figure 44. 144-lead lqfp_ep lead configuration (bottom view) lead 1 lead 3 6 lead 10 8 lead 7 3 lead 144 lead 109 lead 3 7 lead 72 lead 1 indicator ad s p-21 3 6x 144-lead lqfp_ep top view lead 10 8 lead 7 3 lead 1 lead 3 6 lead 109 lead 144 lead 72 lead 3 7 lead 1 indicator gnd pad (lead 145) ad s p-21 3 6x 144-lead lqfp_ep bottom view
rev. g | page 48 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 136-ball bga pin configurations the following table shows the pr ocessors ball names and, when applicable, their default function after reset in parentheses. table 46. bga pin assignments ball name ball no. ball name ball no. ball name ball no. ball name ball no. clk_cfg0 a01 clk_cfg1 b01 boot_cfg1 c01 v ddint d01 xtal a02 gnd b02 boot_cfg0 c02 gnd d02 tms a03 v ddext b03 gnd c03 gnd d04 tck a04 clkin b04 gnd c12 gnd d05 tdi a05 trst b05 gnd c13 gnd d06 resetout a06 a vss b06 v ddint c14 gnd d09 tdo a07 a vdd b07 gnd d10 emu a08 v ddext b08 gnd d11 mosi a09 spiclk b09 gnd d13 miso a10 reset b10 v ddint d14 spids a11 v ddint b11 v ddint a12 gnd b12 gnd a13 gnd b13 gnd a14 gnd b14 v ddint e01 flag1 f01 ad7 g01 ad6 h01 gnd e02 flag0 f02 v ddint g02 v ddext h02 gnd e04 gnd f04 v ddext g13 dai_p18 (sd5b) h13 gnd e05 gnd f05 dai_p19 (sclk5) g14 dai_p17 (sd5a) h14 gnd e06 gnd f06 gnd e09 gnd f09 gnd e10 gnd f10 gnd e11 gnd f11 gnd e13 flag2 f13 flag3 e14 dai_p20 (sfs5) f14
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 49 of 56 | march 2011 figure 45 and figure 46 show bga pin assignments from the bottom and top, respectively. note : use the center block of grou nd pins to provide thermal pathways to your printed circuit boards ground plane. ad5 j01 ad3 k01 ad2 l01 ad0 m01 ad4 j02 v ddint k02 ad1 l02 wr m02 gnd j04 gnd k04 gnd l04 gnd m03 gnd j05 gnd k05 gnd l05 gnd m12 gnd j06 gnd k06 gnd l06 dai_p12 (sd3b) m13 gnd j09 gnd k09 gnd l09 dai_p13 (sclk3) m14 gnd j10 gnd k10 gnd l10 gnd j11 gnd k11 gnd l11 v ddint j13 gnd k13 gnd l13 dai_p16 (sd4b) j14 dai_p15 (sd4a) k14 dai_p14 (sfs3) l14 ad15 n01 ad14 p01 ale n02 ad13 p02 rd n03 ad12 p03 v ddint n04 ad11 p04 v ddext n05 ad10 p05 ad8 n06 ad9 p06 v ddint n07 dai_p1 (sd0a) p07 dai_p2 (sd0b) n08 dai_p3 (sclk0) p08 v ddext n09 dai_p5 (sd1a) p09 dai_p4 (sfs0) n10 dai_p6 (sd1b) p10 v ddint n11 dai_p7 (sclk1) p11 v ddint n12 dai_p8 (sfs1) p12 gnd n13 dai_p9 (sd2a) p13 dai_p10 (sd2b) n14 dai_p11 (sd3a) p14 table 46. bga pin assignments (continued) ball name ball no. ball name ball no. ball name ball no. ball name ball no.
rev. g | page 50 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 figure 45. bga pin assignme nts (bottom view, summary) a vss v ddint v ddext i/o signals a vdd gnd key 1 2 3 4 5 6 7 8 9 10 11 12 14 13 p n m l k j h g f e d c b a figure 46. bga pin assignments (top view, summary) a vss v ddint v ddext i/o signals a vdd gnd key 123456789101112 14 13 p n m l k j h g f e d c b a
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 51 of 56 | march 2011 package dimensions the processor is available in 136-ball bga and 144-lead exposed pad (lqfp_ep) packages. figure 47. 144-lead low profile quad flat package, exposed pad [lqfp_ep] (sw-144-1) dimensions shown in millimeters compliant to jedec standards ms-026-bfb-hd *exposed pad is coincident with bottom surface and does not protrude beyond it. exposed pad is centered. 0.15 0.05 0.08 coplanarity 1.45 1.40 1.35 7 3.5 0 0.20 0.09 view a rotated 90 ccw 0.27 0.22 0.17 0.75 0.60 0.45 0.50 bsc lead pitch 20.20 20.00 sq 19.80 22.20 22.00 sq 21.80 top view (pins down) bottom view (pins up) exposed* pad 1 36 1 36 37 73 72 37 72 108 73 108 144 109 144 109 pin 1 1.60 max seating plane view a 8.80 sq
rev. g | page 52 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 surface-mount design table 47 is provided as an aid to pcb design. for industry stan- dard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 48. 136-ball chip scale package ball grid array [csp_bga] (bc-136) dimensions shown in millimeters * compliant with jedec standards mo-205-ae with exception to ball diameter. 0.25 min detail a * 0.50 0.45 0.40 ball diameter 0.12 max coplanarity 0.80 bsc 10.40 bsc sq a b c d e f g j h k l m 12 13 14 11 10 8 7 6 3 2 1 95 4 1.31 1.21 1.10 a1 corner index area 1.70 max top view ball a1 indicator detail a bottom view n p 12.10 12.00 sq 11.90 seating plane table 47. bga data for use with surface-mount design package package ball attach type package solder mask opening package ball pad size 136-ball csp_bga (bc-136) solder mask defined 0.40 mm diameter 0.53 mm diameter
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 53 of 56 | march 2011 automotive products some adsp-2136x models are avai lable for automotive applica- tions with controlled manufactur ing. note that these special models may have specifications that differ from the general release models. the automotive grade products shown in table 48 are available for use in automotive applications. contact your local adi account representative or authorized adi product distributor for specific product ordering info rmation. note that all automo- tive products are rohs compliant. table 48. automotive products model notes temperature range 1 instruction rate on-chip sram rom package description package option ad21362wbbcz1xx 2 C40oc to 85oc 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 ad21362wbswz1xx 2 C40oc to 85oc 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21362wyswz2xx 2 C40oc to 105oc 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21363wbbcz1xx C40oc to 85oc 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 ad21363wbswz1xx C40oc to 85oc 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21363wyswz2xx C40oc to 105oc 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21364wbbcz1xx C40oc to 85oc 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 ad21364wbswz1xx C40oc to 85oc 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21364wyswz2xx C40oc to 105oc 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21365wbswz1xxa 3, 4 C40oc to 85oc 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21365wbswz1xxf 3, 4 C40oc to 85oc 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 AD21365WYSWZ2XXA 3, 4 C40oc to 105oc 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21366wbbcz1xxa 3, 4 C40oc to 85oc 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 ad21366wbswz1xxa 3, 4 C40oc to 85oc 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 ad21366wyswz2xxa 3, 4 C40oc to 105oc 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 1 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 14 for junction temperature (t j ) specification which is the on ly temperature specification. 2 license from dtla required for these products. 3 available with a wide variety of audio algorithm combinations so ld as part of a chipset and bund led with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. 4 license from dolby laboratories, in c., and digital theater systems (d ts) required for these products.
rev. g | page 54 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 ordering guide model 1 1 z = rohs compliant part. notes temperature range 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a specification. please see operating conditions on page 14 for junction temperature (t j ) specification which is the on ly temperature specification. instruction rate on-chip sram rom package description package option adsp-21362bbcz-1aa 3 3 license from dtla required for these products. C40c to +85c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21362bswz-1aa 3 C40c to +85c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21362yswz-2aa 3 C40c to +105c 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21363kbc-1aa 0c to +70c 333 mhz 3 m bit 4m bit 136-ball csp_bga bc-136 adsp-21363kbcz-1aa 0c to +70c 333 mh z 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21363kswz-1aa 0c to +70c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21363bbc-1aa C40c to +85c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21363bbcz-1aa C40c to +85c 333 mh z 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21363bswz-1aa C40c to +85c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21363yswz-2aa 4 4 license from dolby laboratories, inc., and digital theater systems (d ts) required for these products. C40c to +105c 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21364kbc-1aa 0c to +70c 333 mhz 3 m bit 4m bit 136-ball csp_bga bc-136 adsp-21364kbcz-1aa 0c to +70c 333 mh z 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21364kswz-1aa 0c to +70c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21364bbcC1aa C40c to +85c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21364bbcz-1aa C40c to +85c 333 mh z 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21364bswz-1aa C40c to +85c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21364yswz-2aa C40c to +105c 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21365bbcz-1aa 3, 4, 5 5 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. C40c to +85c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21365bswz-1aa 3, 4, 5 C40c to +85c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21365yswz-2aa 3, 4, 5 C40c to +105c 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21365yswz-2ca 3, 4, 5 C40c to +105c 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21366kbc-1aa 4, 5 0c to +70c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21366kbcz-1ar 4, 5, 6 6 r = tape and reel. 0c to +70c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21366kbcz-1aa 4, 5 0c to +70c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21366kswz-1aa 4, 5 0c to +70c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21366bbcC1aa 4, 5 C40c to +85c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21366bbcz-1aa 4, 5 C40c to +85c 333 mhz 3m bit 4m bit 136-ball csp_bga bc-136 adsp-21366bswz-1aa 4, 5 C40c to +85c 333 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1 adsp-21366yswz-2aa 4, 5 C40c to +105c 200 mhz 3m bit 4m bit 144-lead lqfp_ep sw-144-1
adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 rev. g | page 55 of 56 | march 2011
rev. g | page 56 of 56 | march 2011 adsp-21362/adsp-21363/adsp-21364/adsp-21365/adsp-21366 ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06359-0-3/11(g)

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